Generally, in a computer system, power for a central processing unit (CPU) is not directly provided by a power supply, mainly because the core current (Icore) needed by the CPU is changed according to the load of the CPU. Thus, the core current (Icore) needed by the CPU may increase or decrease instantly, and the power supply cannot give such quick response. To solve the problem, a switching power circuit for supplying power to the CPU is disposed on a motherboard.
FIG. 1 is a schematic diagram showing the switching power circuit on the motherboard of a conventional computer. As shown in FIG. 1, the switching power circuit mainly includes a pulse width modulation (PWM) control unit 10, a PWM driving unit 12 and a PWM circuit 14.
The PWM control unit 10 may output a PWM signal to the PWM driving unit 12.
The PWM driving unit 12 may generate a first driving signal S1 and a second driving signal S2 according to the PWM signal.
In addition, the PWM circuit 14 includes a high side MOS M1, a low side MOS M2, an output inductance Lo and an output capacitor Co. A drain (D) of the high side MOS M1 is connected to a power voltage (Vcc), the gate (G) of the high side MOS M1 receives the first driving signal S1, a source (S) of the high side MOS M1 is connected to a first terminal of the output inductance Lo. A drain (D) of the low side MOS M2 is connected to the first terminal of the output inductance Lo, and a gate (G) of the low side MOS receives the second driving signal S2. A source (S) of the low side MOS M1 is connected to the ground terminal (GND).
The source (S) of the high side MOS M1 and the drain (D) of the low side MOS M2 may be considered as a phase terminal (P) of the switching power circuit.
A second terminal of the output inductance Lo is an output terminal of the core current (Icore). The output capacitor Co is connected between the output terminal of the core current (Icore) and the ground terminal (GND).
The output terminal of the core current (Icore) may be connected to a power layer (not shown) of the motherboard. The power layer is connected to the CPU to provide the core current (Icore) to the CPU. In addition, the high side MOS M1 and the low side MOS M2 are N-MOSFETs, and the power voltage (Vcc) is 19 volts.
The main function of the switching power circuit is to give an instant response and provide steady core current (Icore) to the motherboard according to the voltage level requirement sent by the CPU. These are achieved by the detection of the voltage identification digital (VID) signal of the CPU, and the VID signal has relation to the actual load of the CPU. When the VID signal is detected, the PWM control unit 10 outputs the PWM signal according to the detected VID signal. The PWM driving unit 12 then outputs the first driving signal S1 and the second driving signal S2 according to the received PWM signal. The first driving signal S1 and the second driving signal S2 may control the high side MOS M1 and the low side MOS M2 to be conducted (ON) or blocked (OFF), respectively. Only one of the high side MOS and the low side MOS is conducted (ON) at the same time.
For example, when the PWM control unit 10 knows that the CPU is in a heavy load condition according to the detected VID signal, it outputs the PWM signal to make the PWM driving unit 12 output a first driving signal S1 to prolong the conducting time of the high side MOS M1. That is, the PWM driving unit 12 outputs a second driving signal S2 to prolong the blocking time of the low side MOS M2. The phase terminal (P) of the switching power circuit may output core current (Icore) with larger value via the power voltage (Vcc) to the output terminal of the core current (Icore) to improve the processing efficiency of the CPU. On the contrary, when the PWM control unit 10 knows the CPU is in a light load condition according to the detected VID signal, the output PWM signal may make the PWM driving unit 12 output the first driving signal S1 to prolong the blocking time of the high side MOS M1. That is, the PWM driving unit 12 outputs a second driving signal S2 to prolong the conducting time of the low side MOS M2. The phase terminal (P) of the switching power circuit may output core current (Icore) with lower value via the power voltage (Vcc) to the output terminal of the core current (Icore) to reduce the power consumed by the CPU. The output inductance Lo is used as a power storing and rectifying component, and it may store excessive power temporarily when the current is large or release power when the current is not enough to make the current steady. The output capacitor Co is used as an electric power storing and wave filtering component, and it is not only able to exclude low frequency noises, but also able to store current to provide steady power to the CPU.
Since the peripheral components on the motherboard may generate parasitic inductance, when the high side MOS M1 is conducted (ON) instantly, the high side MOS M1 may generate instant current with a larger value. Furthermore, since the voltage generated by the parasitic inductance is Vp1=L*di/dt, the Vp1 increases instantly, and a voltage spike is generated. Wherein, the Vp1 is the spike voltage generated by the parasitic inductance, L is the inductance value of the parasitic inductance, and i is the value of the current passing through the parasitic inductance. The excessive spike voltage may damage the power components of the switching power circuit.
FIG. 2 is a schematic diagram, showing the output voltage of the phase terminal (P) of the switching power circuit.
As shown in FIG. 2, at the time point t1, the high side MOS M1 is conducted (ON) instantly. At that moment, the phase terminal (P) begins to output voltage (Vlow, the output voltage of the phase terminal (P) before the high side MOS is conducted).
At the time segment between t1 and t2, the output voltage of the phase terminal (P) increases continuously.
At the time point t2, a spike is generated.
At the time point t3, the spike reaches the maximum value (Vspike-max).
At the time point t3 to t4, the spike decreases continuously.
At the time point t4, the spike disappears. The output voltage of the phase terminal (P) of the switching power circuit reaches steady-state voltage (Vhigh, the output voltage of the phase terminal (P) in a steady state after the high side MOS M1 is conducted).
To prevent the excessive spike voltage (or spike current) from damaging the power components of the switching power circuit, a snubber circuit is usually used. FIG. 3 is a schematic diagram showing a conventional switching power circuit. As shown in FIG. 3, the difference between FIG. 1 and FIG. 3 is that the phase terminal (P) of the switching power circuit in FIG. 3 is connected to a snubber circuit 16 in a parallel connecting mode. The snubber circuit 16 further includes a resistor (Rs) and a capacitor (Cs). A first terminal of the resistor (Rs) is connected to the phase terminal (P), and a second terminal of the resistor (Rs) is connected to a first terminal of the capacitor (Cs). A second terminal of the capacitor (Cs) is connected to the ground terminal.
When the high side MOS M1 is conducted (ON) and the low side MOS M2 is blocked (OFF), the voltage (Vds) of the phase terminal (P) begins to increase. An input current (Iinput) generated by the power voltage (Vcc) may charge the capacitor (Cs) via the resistor (Rs). When the high side MOS M1 is blocked (OFF) and the low side MOS M2 is conducted (ON), power stored in the capacitor (Cs) is discharged via the low side MOS M2 and the resistor (Rs). Since the snubber circuit 16 may consume part of the spike power, power consumed in the power components is reduced. Thus, the objective of protecting is achieved. The charging and discharging time of the snubber circuit 16 depend on the value of the resistor (Rs) and the value of the capacitor (Cs). Generally, the value of the resistor (Rs) is dozens of to hundreds of ohms, and the value of the capacitor (Cs) is hundreds of pFs to dozens of nFs.
As shown in FIG. 2, since the conventional snubber circuit 16 is not only able to absorb power generated by the spike (at the time segment between t2 and t4), it is also able to absorb power generated before the spike is generated and after the phase terminal (P) begins to output voltage (at the time segment between t1 and t2). It wastes power.